The present invention relates generally to the formation of integrated circuit structures, and particularly to methods for forming novel BARC opens for precision critical dimension control.
As semiconductor wafers continually progress to higher density chips with shrinking geometries of 0.13 μm and below, the materials and processes used in wafer fabrication are undergoing dramatic changes. There is a concurrent scaling of all device features to maintain electrical performance. This trend is made possible by the development of new manufacturing techniques as well as innovative improvements of existing procedures thereby extending their utility further towards miniaturization and higher density.
One area where the limits of technology are constantly tested is the formation of contact and via openings in insulating or dielectric layers on semiconductor substrates. These openings pass through the various dielectric layers and are filled with a metal, such as tungsten to form an electrical connection at the silicon surface between the devices in the silicon wafer and the first metal layer in the case of contacts; and, in the case of vias, they form an electrical pathway from one metal layer to the metal layer either above or below it.
Contact and via openings having submicron geometries represent one of the smallest microlithographically defined features on the integrated circuit. The openings are typically formed by anisotropic etching through the insulating layer using a patterned photoresist mask and can provide deep vertical openings having high-aspect ratios (ratio of height to width for an opening).
One desirable etch sidewall profile for submicron feature sizes is an anisotropic profile, where the rate of etching is in only one direction perpendicular to the wafer surface. As there is very little lateral etching activity, the benefit is that this leaves vertical sidewalls, permitting a higher packing density of etched features on the chip. Anisotropic etch is critical for the patterning of submicron devices with small linewidths and features. Advanced IC applications usually require 88 to 89° vertical sidewall profiles.
One goal of anisotropic etching is to reproduce the image of a mask on the wafer surface with a high degree of integrity to ensure critical dimension and profile control. Unfortunately, several drawbacks may occur in the formation of contact and via openings as a result of anisotropic etching. One such drawback is the occurrence of etch bias, which is a measure of the change in linewidth or space of a critical dimension (CD) after performing an etch process. It is usually caused by undercutting and/or overetching which occur when the etch process removes excessive material below the mask, causing the top surface of the etched film to be recessed from the resist edge.
Additionally, current photolithography tools may not be able to achieve the high resolution critical for 0.12 μm or below wafer features such as contact or via openings
and these tools are unable to reduce photoresist degradation during the anisotropic etching process.
Further, there is the high cost associated with the use of photolithography equipment such as lens, scanner and stepper tools. Photolithography require lens with higher numerical aperture (NA) to achieve better resolution for deep submicron features. However, higher numerical aperture lens require the purchase of current model scanner tools which will lead to higher costs.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for a method of controlling the critical dimensions in the formation of contact, via and damascene openings in insulating or dielectric layers on wafers.